Recently, demand for portable devices such as mobile telephones, portable music players, and digital still cameras increases year by year. Since these portable devices are battery-driven, low power consumption is particularly required of LSI used in circuit portions of the portable devices. Further, to achieve cost reductions by reducing heat generating elements, lower power consumption is similarly demanded of LSI in stationary devices.
A multiple power source LSI has been developed to address such demands for lower LSI power consumption. The multiple power source LSI includes multiple modules of power supply domains in the LSI. Therefore, a circuit requiring high-speed operation is disposed in a module supplying a higher voltage and a circuit not requiring high-speed operation is disposed in a module supplying a lower voltage. Thereby, the multiple power source LSI may execute processes satisfying requested performance and achieve lower power consumption.
On the other hand, semiconductor integrated circuits tend to have a longer signal delay time of elements due to manufacturing variations and increased variations in the leakage current accompanying the miniaturization of minimum processing dimensions. If a constant voltage is supplied regardless of the variations of element characteristics, a semiconductor integrated circuit having large manufacturing variation is unable to satisfy an objective operation frequency when the element delay is shifted to a value greater than the design value. When the element delay is shifted to a smaller value, the leak current of the element increases and power consumption increases as a result.
A technique of preventing the increase in the leak current due to process variation is known as an adaptive supply voltage (ASV) technique of adaptively adjusting the power supply voltage depending on the process variation while satisfying an objective operation frequency (see e.g., Tshanz, J.; Narendra, S.; Nair, R.; and De, V., “Effectiveness of Adaptive Supply Voltage and Body Bias for Reducing Impact of Parameter Variations in Low Power and High Performance Microprocessors”, IEEE J. Solid-State Circ. Vol. 38, No. 5, pp. 826-829, May 2003).
FIG. 16 is an explanatory diagram of a principle of achieving lower power consumption with the ASV technique. A chart 1601 of FIG. 16 indicates the dependencies of the power consumption on manufacturing variation and the critical path delay for a fixed power supply voltage. A chart 1602 of FIG. 16 indicates the dependencies of the power consumption on manufacturing variation and the critical path delay for the ASV technique.
As depicted in the chart 1601, a chip supplied with a fixed power supply voltage under the fast manufacturing variation condition is supplied with a voltage that is more than necessary regardless of low critical path delay. This excessive supply of the power supply voltage increases the leakage current, resulting in an increase in the power consumption. Therefore, as depicted in the chart 1602, if the power supply voltage is adjusted to be reduced as much as possible within a range of the critical path satisfying the objective operation frequency according to the manufacturing variation, the power consumption may be reduced unless a chip has the slow manufacturing variation condition.
Such an ASV technique is applicable not only to an LSI made up of a single power supply domain module but also to a multiple power source LSI made up of multiple power supply domain modules, for example, by allocating the process variation and the power supply voltage as parameters and performing a delay analysis such as static timing analysis (STA) to obtain the ASV.
FIG. 17 is a block diagram of an exemplary configuration of a conventional single power source LSI. FIG. 18 is a block diagram of an exemplary configuration of a conventional multiple power source LSI. Although a single power supply LSI 1700 may be adjusted through power supply to a power supply domain A by the ASV technique as above, a multiple power supply (triple power supply) LSI 1800 is adjusted appropriately through power supply voltages to power supply domains by the ASV technique taking into consideration logical paths within and between power supply domains A, B, and C.
A circuit has been disclosed that uses a selector to switch a clock signal output from a PLL circuit to suppress clock skew generated when the power supply voltage is changed in some of the cores (see e.g., Japanese Laid-Open Patent Publication No. 2005-100269). A circuit has also been disclosed that, to eliminate malfunction, enables operation voltage sources to be individually set for a first group of circuits that generate clock signals and a second group of circuits that transfer signals and execute logical processing operations according to the clock signals (see e.g., Japanese Patent Application Laid-Open Publication No. 2002-312058).
However, the technology disclosed in Japanese Laid-Open Patent Publication No. 2005-100269 is not suitable for a multiple power source LSI having multiple power supply domains. In the case of a multiple power source LSI, a circuit may be configured across power supply domains of different voltages. When a power supply voltage is obtained according to process variations in the multiple power source LSI, consideration may be given to combinations for each type of the power supply voltages. Therefore, as compared to the single power supply LSI, the number of processes for obtaining the power supply voltage increases considerably.
For example, assuming that the process variation conditions are J conditions, the power supply voltage conditions are K conditions, and the number of power supply domains is L, to obtain the ASV of the power supply domains, the number of times I delay analysis is performed may be expressed by equation (1).I (number of times delay analysis performed)=J×KL [times]  (1)
Therefore, the number of times delay analysis is performed exponentially increases as the number of power supply domains increases, arising in a problem of heavy processing load on the functional part obtaining the ASV.
Although the clock skew (mismatch of clock timings) of the power supply domains of the multi power supply LSI may be corrected according to Japanese Laid-Open Patent Publication No. 2005-100269, the power supply voltage is not automatically adjustable according to process variations. Similarly, with Japanese Patent Application Laid-Open Publication No. 2002-312058, although the operation voltage sources are individually settable for the first group of circuits that generate clock signals and the second group of circuits that transfer signals and execute logical processing operations according to the clock signals, the power supply voltage is not automatically adjustable according to process variations.
When the ASV of a multiple power source LSI is obtained, the manufacturing variation dependency and the power supply voltage dependency may be different for delay times of a clock tree circuit and a logic circuit due to factors such as a RAM macro, different logic cells, and different transistor types, for example. If the manufacturing variation dependency and the power supply voltage dependency are different for delay times of the clock tree circuit and the logic circuit, malfunction may occur even when the clock skew is corrected.
FIG. 19 is an explanatory diagram of delay times of a clock tree path and a logic path. A chart 1901 of FIG. 19 depicts an example in which the manufacturing variation dependency and the power supply voltage dependency are similar for the delay times of the clock tree circuit and the logic circuit. In such a case, the logic path may be operated at the objective operation frequency by obtaining the AVS based on the characteristics of the clock tree path.
However, if the manufacturing variation dependency and the power supply voltage dependency are different for delay times of the clock tree circuit and the logic circuit, behavior different from the chart 1901 is exhibited. A chart 1902 depicts an example in which the dependency of the logic path delay is smaller. A chart 1903 depicts an example in which the dependency of the logic path delay is greater.
As depicted in charts 1802 and 1803, the manufacturing variation dependency and the power supply voltage dependency may be different for delay times of the clock tree path and the logic path, and the difference may not be negligible in many cases. In particular, as depicted in the chart 1903, when the manufacturing variation dependency of the logic path is greater, if the AVS is obtained based on the characteristics of the clock tree path, a problem arises in that the logic path is unable to operate at the objective operation frequency, causing malfunction.